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? xicor, inc. 2000 patents pending 2000-4003 9/6/00 ep characteristics subject to change without notice. 1 of 18 1m x28lv010 128k x 8 bit 3.3 volt, byte alterable e 2 prom features access time: 70, 90, 120, 150ns simple byte and page write single 3.3v?0% supply no external high voltages or v pp control circuits self-timed no erase before write no complex programming algorithms no overerase problem low power cmos active: 20ma standby: 20? software data protection protects data against system level inadvertant writes high speed page write capability highly reliable direct write cell endurance: 100,000 write cycles data retention: 100 years early end of write detection ? a t a polling toggle bit polling description the xicor x28lv010 is a 128k x 8 e 2 prom, fabri- cated with xicor's proprietary, high performance, ?at- ing gate cmos technology. like all xicor programmable non-volatile memories the x28lv010 requires a single voltage supply. the x28lv010 fea- tures the jedec approved pinout for byte-wide memo- ries, compatible with industry standard eproms. the x28lv010 supports a 256-byte page write opera- tion, effectively providing a 12?/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. the x28lv010 also features d a t a polling and toggle bit polling, system software support schemes used to indicate the early completion of a write cycle. in addition, the x28lv010 supports software data protection option. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. data retention is speci?d to be greater than 100 years. block diagram x buffers latches and decoder i/o buffers control logic and timing 1m-bit e 2 prom array i/o 0 ?/o 7 data inputs/outputs ce oe v cc v ss a 8 ? 16 we a 0 ? 7 y buffers latches and decoder and latches
x28lv010 characteristics subject to change without notice. 2 of 18 pin configurations 232 43 31 nc a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28lv010 pdip x28lv010 (top view) a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 a 14 i/o 7 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 a 16 nc v cc we nc 6 1 5 8 7 9 10 11 12 13 15 17 16 18 1920 22 23 24 25 26 27 28 29 oe ce a 7 14 21 30 plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 x28lv010 oe a 10 ce nc nc v ss nc nc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 a 11 a 9 a 8 a 13 a 14 nc nc nc we v cc nc nc nc a 16 a 15 a 12 a 7 a 6 a 5 tsop 20 21 a 4 a 15 a 12 a 13 a 8 a 9 a 11 a 10 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 a 0 a 1 a 2 a 3 i/o 2 i/o 1 i/o 0 pin descriptions addresses (a 0 ? 16 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power con- sumption is reduced. output enable (oe ) the output enable input controls the data output buff- ers and is used to initiate read operations. data in/data out (i/o 0 ?/o 7 ) data is written to or read from the x28lv010 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the x28lv010. pin names device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control architecture eliminates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. symbol description a 0 ? 16 address inputs i/o 0 ?/o 7 data input/output we write enable ce chip enable oe output enable v cc +3.3v v ss ground nc no connect
x28lv010 characteristics subject to change without notice. 3 of 18 write write operations are initiated when both ce and we are low and oe is high. the x28lv010 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs ?st. a byte write operation, once initiated, will automatically continue to comple- tion, typically within 5ms. page write operation the page write feature of the x28lv010 allows the entire memory to be written in 2.5 seconds. page write allows two to two hundred ?ty-six bytes of data to be consecutively written to the x28lv010 prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 8 through a 16 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte write cycle, the host can write an additional one to two hundred ?ty ?e bytes in the same manner as the ?st byte was written. each successive byte load cycle, started by the we high to low transition, must begin within 100? of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100?, the internal automatic programming cycle will commence. there is no page write window limitation. effectively the page write window is in?itely wide, so long as the host continues to access the device within the byte load cycle time of 100?. write operation status bits the x28lv010 provides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. figure 1. status bit assignment data polling (i/o 7 ) the x28lv010 features d a t a polling as a method to indicate to the host system that the byte write or page write cycle has completed. d a t a polling allows a sim- ple bit test operation to determine the status of the x28lv010, eliminating additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read the last byte written will pro- duce the complement of that data on i/o 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will re?ct true data. note: if the x28lv010 is in the protected state and an illegal write operation is attempted d a t a polling will not operate. toggle bit (i/o 6 ) the x28lv010 also provides another method for deter- mining when the internal write cycle is complete. dur- ing the internal programming cycle, i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. 5 tb dp 43210 i/o reserved toggle bit data polling
x28lv010 characteristics subject to change without notice. 4 of 18 data polling i/o 7 figure 2. data polling bus sequence ce oe we i/o 7 x28lv010 last write high z v ol v ih a 0 ? 14 an an an an an an v oh an ready figure 3. data polling software flow d a t a polling can effectively halve the time for writing to the x28lv010. the timing diagram in figure 2 illus- trates the sequence of events on the bus. the software ?w diagram in figure 3 illustrates one method of implement-ing the routine. write data save last data and address read last address io 7 compare? no yes no yes writes complete? ready x28lv010
x28lv010 characteristics subject to change without notice. 5 of 18 the toggle bit i/o 6 figure 4. toggle bit bus sequence ce oe we i/o 6 x28lv010 v oh v ol last write high z ready figure 5. toggle bit software flow the toggle bit can eliminate the software housekeep- ing chore of saving and fetching the last address and data written to a device in order to implement d a t a polling. this can be especially helpful in an array com- prised of multiple x28lv010 memories that is fre- quently updated. toggle bit polling can also provide a method for status checking in multiprocessor applica- tions. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software ?w dia- gram in figure 5 illustrates a method for polling the toggle bit. hardware data protection the x28lv010 provides three hardware features that protect nonvolatile data from inadvertent writes. noise protection? we pulse less than 10ns will not initiate a write cycle. default v cc sense?ll functions are inhibited when v cc is 2.5v. write inhibit?olding either oe low, we high, or ce high will prevent an inadvertent write cycle dur- ing power-up and power-down, maintaining data integrity. software data protection the x28lv010 offers a software controlled data pro- tection feature. the x28lv010 is shipped from xicor with the software data protection not enabled: that is the device will be in the standard operating mode. in this mode data should be protected during power-up/ -down operations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. load accum from addr n compare accum with addr n ready no yes last write compare ok?
x28lv010 characteristics subject to change without notice. 6 of 18 the x28lv010 can be automatically protected during power-up and power-down without the need for exter- nal circuits by employing the software data protection feature. the internal software data protection circuit is enabled after the ?st write operation utilizing the soft- ware algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28lv010 is also protected from inadvertent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three speci? addresses. refer to figures 6 and 7 for the sequence. the three byte sequence opens the page write window enabling the host to write from one to two hundred ?ty- six bytes of data. once the page load cycle has been completed, the device will automatically be returned to the data protected state. software data protection figure 6. timing sequence?yte or page write ce we (v cc ) write protected v cc 0v data addr aa 5555 55 2aaa a0 5555 t blc max writes ok byte or page t wc
x28lv010 characteristics subject to change without notice. 7 of 18 figure 7. write sequence for software data protection regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the x28lv010 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the x28lv010 will be write protected during power-down and after any sub- sequent power-up. the state of a 15 and a 16 while exe- cuting the algorithm is don? care. note: once initiated, the sequence of write operations should not be interrupted. write last byte to last address write data 55 2aaa write data a0 5555 write data xx to any address after t wc re-enters data protected state write data aa to address 5555 byte/page load operation optional to address to address resetting software data protection figure 8. reset software data protection timing sequence ce we standard operating mode v cc data addr aa 5555 55 2aaa 80 5555 t wc aa 5555 55 2aaa 20 5555
x28lv010 characteristics subject to change without notice. 8 of 18 figure 9. software sequence to deactivate software data protection in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an e 2 prom programmer, the following six step algo- rithm will reset the internal protection circuit. after t wc , the x28lv010 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. system considerations because the x28lv010 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipa- tion and eliminate the possibility of contention where multiple i/o pins share the same bus. to gain the most bene? it is recommended that ce be decoded from the address bus and be used as the pri- mary device selection input. both oe and we would then be common among all devices in the array. for a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. because the x28lv010 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause tran- sient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of the i/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be sup- pressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recom- mended that a 0.1? high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended that a 4.7? electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage drop caused by the inductive effects of the pc board traces. 2aaa write data 55 2aaa write data 80 5555 5555 write data 20 5555 write data aa to address 5555 to address to address write data aa to address write data 55 to address to address
x28lv010 characteristics subject to change without notice. 9 of 18 absolute maximum ratings temperature under bias x28lv010 ....................................... ?0? to +85? x28lv010i .................................... ?5? to +135? storage temperature ........................ ?5? to +150? voltage on any input pins (including nc pins) with respect to ground .......... ?.5 to 6.25v voltage on any output pins with respect to ground .........................?.5 to v cc +0.5v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. recommend operating conditions temperature min. max. commercial 0? +70? industrial ?0? +85? supply voltage limits x28lv010 3.3v ?0% d.c. operating characteristics (over the recommended operating conditions, unless otherwise speci?d.) notes: (1) v il min. and v ih max. are for reference only and are not tested. power-up timing capacitance t a = +25?, f = 1mhz, v cc = 5v symbol parameter limits units test conditions min. max. i cc v cc current (active) (ttl inputs) 20 ma ce = oe = v il , we = v ih , all i/o? = open, address inputs = .4v/2.4v levels @ f = 10mhz i sb2 v cc current (standby) (cmos inputs) com. 20 ? ce = v cc ?0.3v, oe = v il , all i/o? = open, other inputs = v cc ind. 50 ? i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc , ce = v ih v ll (1) input low voltage 0.5 0.8 v v lh (1) input high voltage 2 v cc + 0.3 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage 2.4 v i oh = ?00? symbol parameter max. units t pur (2) power-up to read operation 100 ? t puw (2) power-up to write operation 5 ms symbol parameter max. units test conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 10 pf v in = 0v
x28lv010 characteristics subject to change without notice. 10 of 18 endurance and data retention notes: (2) this parameter is periodically sampled and not 100% tested. parameter min. max. units endurance (2) 10,000 cycles per byte endurance (2) 100,000 cycles per page data retention (2) 100 years a.c. conditions of test mode selection equivalent a.c. load circuit symbol table input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v ce oe we mode i/o power l l h read d out active l h l write d in active hx x standby and write inhibit high z standby x l x write inhibit x x h write inhibit 3.3v 1.92k ? 100pf output 1.37k ? waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x28lv010 characteristics subject to change without notice. 11 of 18 a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) read cycle limits notes: (3) t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf, from the point when ce or oe return high (whichever occurs ?st) to the time when the outputs are no longer driven. read cycle symbol parameter x28lv010-70 x28lv010-90 x28lv010-120 x28lv010-150 units min. max. min. max. min. max. min. max. t ce chip enable access time 70 90 120 150 ns t aa address access time 70 90 120 150 ns t oe output enable access time 35 40 40 40 ns t lz (3) ce low to active output 0 0 0 0 ns t olz (3) oe low to active output 0 0 0 0 ns t hz (3) ce high to high z output 40 50 50 50 ns t ohz (3) oe high to high z output 40 50 50 50 ns t oh output hold from address change 00 0 0ns t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid
x28lv010 characteristics subject to change without notice. 12 of 18 write cycle limits notes: (4) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum tim e the device requires to complete internal write operation. we controlled write cycle symbol parameter min. max. units t wc (4) write cycle time 5 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 50 ns t oes oe high setup time 0 ns t oeh oe high hold time 0 ns t wp we pulse width 50 ns t wph we high recovery 50 ns t ds data setup 50 ns t dh data hold 10 ns t dw delay to next write 10 ? t blc byte load cycle 0.2 100 ? address t as t wc t ah t oes t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp t wph
x28lv010 characteristics subject to change without notice. 13 of 18 ce controlled write cycle page write cycle notes: (5) between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively per- forming a polling operation. (6) the timings shown above are unique to page write operations. individual byte load operations within the page write must conf orm to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t wph t cs t ds t dh t ch ce we oe high z data valid t cw data in data out we oe (5) last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address * (6) i/o *for each successive write within the page write operation, a 8 ? 16 should be the same or writes to an unknown address could occur.
x28lv010 characteristics subject to change without notice. 14 of 18 data polling timing diagram (7) toggle bit timing diagram notes: (7) polling operations are by de?ition read cycles and are therefore subject to read cycle timings. address an d in = x d out = x t wc t oeh an an ce we oe i/o 7 t dw t oes d out = x ce oe we i/o 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary.
x28lv010 characteristics subject to change without notice. 15 of 18 packaging information 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) typ. typ. 0.017 (0.43) 0.045 (1.14) x 45 0.300 (7.62) ref. 0.453 (11.51) 0.447 (11.35) typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) typ. 0.490 (12.45) pin 1 0.400 (10.16) ref. 0.553 (14.05) 0.547 (13.89) typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) typ. 0.590 (14.99) 3 typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) seating plane 0.004 lead co ?planarity 32-lead plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only 0.510" typical 0.050" typical 0.050" typical 0.300" ref. foo tprint 0.400" 0.410" 0.030" typical 32 places
x28lv010 characteristics subject to change without notice. 16 of 18 packaging information 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.160 (4.06) 0.125 (3.17) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.665 (42.29) 1.644 (41.76) 1.500 (38.10) ref. pin 1 index 0.160 (4.06) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.070 (17.78) 0.030 (7.62) 0.557 (14.15) 0.510 (12.95) 0.085 (2.16) 0.040 (1.02) 0 15 32-lead plastic dual in-line package type p typ. 0.010 (0.25) notes:
x28lv010 characteristics subject to change without notice. 17 of 18 packaging information note: all dimensions are shown in millimeters (inches in parentheses). 0.50 ?0.04 (0.0197 ?0.0016) 0.30 ?0.05 (0.012 ?0.002) 14.80 ?0.05 (0.583 ?0.002) 1.30 ?0.05 (0.051 ?0.002) 0.17 (0.007) 0.03 (0.001) typical 40 places 15 eq. spc.@ 0.50 ?0.04 0.0197 0.016 = 9.50 ?0.06 (0.374 ?0.0024) overall tol. non-cumulative solder footprint 0.396 (10.058) 0.392 (9.957) 0.493 (12.522) 0.483 (12.268) pin #1 ident o 0.040 (1.016) o 0.030 (0.762) 1 (0.038) 0.045 (1.143) 0.035 (0.889) 0.0025 (0.065) 0.557 (14.148) 0.547 (13.894) seating plane a 0.007 (0.178) 0.040 (1.016) 15?typ. 0.0197 (0.500) 0.048 (1.219) 0.010 (0.254) 0.006 (0.152) 0.017 (0.432) 0.032 (0.813) typ. 0.017 (0.432) 0.020 (0.508) typ. 0.006 (0.152) detail a 40-lead thin small outline package (tsop) type t 0.965 x 0.005 (0.127) dp. 0.003 (0.076) dp. plane seating typ. 4?typ. pads
x28lv010 characteristics subject to change without notice. 18 of 18 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change s peci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information device access time ?0 = 70ns ?0 = 90ns ?2 = 120ns ?5 = 150ns temperature range blank = commercial = 0? to 70? i = industrial = ?0? to +85? package p = 32-lead pdip j = 32-lead plcc t = 40-lead tsop x28lv010 x -x x

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